In a typical digital design flow of designing an integrated circuit, a VHDL or Verilog behavioral description is synthesized to an equivalent gate-level logical netlist, for example, one containing logic gates (such as, AND2, INV, and NOR2) and their interconnections. Following synthesis, a place-and-route tool will place cells corresponding to the logic gates on a regular grid and will connect the cells' pins with metal lines according to a netlist specification. The cells, which contain the geometric shapes implementing the gate logic at the transistor level, are usually taken from a standard library that has been thoroughly tested and characterized. There are numerous possibilities for modifying or replacing cells once the cells have been instantiated in the physical layout so that it would be difficult for the designer to know if the design has been tampered with.
The design is generally sent to a foundry for fabrication typically using a Graphic Database System II (GDSII) standard file format. Generally, the GDSII format is a database file format for data exchange of integrated circuit (IC) layout artwork. More particularly, the GDSII format is a binary file format representing the geometric shapes comprising the standard cell libraries, along with the metal wiring forming the interconnections. The GDSII file may be “flat” or “hierarchical.” An embodiment of an image of a “flat” GDSII file is illustrated in FIG. 1. As illustrated in FIG. 1, the GDSII file may contain only shapes without any library or other cell information. Alternatively, an embodiment of an image of a “hierarchical” GDSII file is illustrated in FIG. 2. As illustrated in FIG. 2, the GDSII file may contain a single copy of the layout for each library cell and provide placement information for instances of each cell in the full design. The different shading properties of FIGS. 1 and 2 correspond to the different physical layers such as polysilicon, contact, first metal, second metal, etc., that are used within the specified foundry process technology.
During fabrication, the shapes in the GDSII file corresponding to each material layer are imprinted on the Silicon wafer via a lithography process. The small size of the features (tens to hundreds of nanometers) compared to the wavelength of light used in the process results in optical distortions that prevent the actual shapes created on the wafer from exactly matching the perfect rectangles and polygons originally drawn. An embodiment of an image of a portion of a first metal layer of a fabricated digital circuit is illustrated in FIG. 3. As illustrated in FIG. 3, the actual shapes created on the wafer are slightly distorted, meaning that the actual shapes are not perfect rectangles and polygons, relative to the shapes as originally drawn in the GDSII file. These distortions may present issues, especially in the context of implementing a process to reverse engineer a fabricated integrated circuit to reveal its original design.
A method of finding locations of standard cells in an integrated circuit is disclosed in U.S. Pat. Nos. 7,643,665; 7,580,557; and 7,873,203 all of which are entitled Method of Design Analysis of Existing Integrated Circuits and issued to Zavadsky et al. (referred to hereinafter as “the '665 patent family”). The '665 patent family discloses a four step process for finding the location of standard cells in an integrated circuit based on images of layers of the integrated circuit. The '665 patent family process is limited to image data and does not take into account other sources of data. More particularly, the '665 patent family process uses distinctive landmarks of the image data, which are pixel amplitude extremes, to obtain points of interest.
According to the '665 patent family process, layers of the integrated circuit are exposed and scanned under high magnification. In the first step of the process, features or points of interest, which are pixel amplitude extremes, of the images are extracted. These pixel amplitude extremes include centers of contacts which are connections between the first conductive layer and the polysilicon layer, vias which are connections between conductive layers, and corners of the polygons representing the lowest conductive layer. Once the points of interest are extracted, the '665 patent family process characterizes each point of interest by building a 32-bit descriptor, which is a grid of 32 non-overlapping rectangles, around each point of interest. If a conductive metal polygon occupies a minimum pre-determined percentage of a rectangle, the rectangle is set to 1; and if no conductive metal polygon occupies the rectangle or it is less than the minimum pre-defined percentage, the rectangle is set to 0. Thus, the '665 patent family process is dependent upon the threshold chosen as the minimum pre-determined percentage for acceptance or non-acceptance. Invariably, there will be situations that are not very clear and in these situations errors may occur.
Further, in the '665 patent family process an operator manually selects the standard cell to be used as the template throughout the comparison process, which can be time consuming and may require the operator to be highly skilled in the area of integrated circuits. More particularly, in the second step of the '665 patent family process, an operator extracts an area of the integrated circuit layout that represents a standard cell, by highlighting or creating a box around a selected area, and indicates that the cell is a standard cell. The standard cell is used as a template and the points of interest in the template are compared to the points of interest within the image.
According to the '665 patent family process, each bit of the 32-bit descriptor of the template point of interest is compared to the corresponding bit of each 32-bit descriptor for each point of interest within the image. Once it has been determined that a point of interest in the image portion is similar to a point of interest on the template, a confidence voting process is conducted. More particularly, the template is superimposed onto portions of the image and the points of interest are compared, wherein votes represent a confidence value of a possible match. Thus, the '665 patent family process is dependent upon the threshold chosen for acceptance or non-acceptance. Invariably, there will be situations that are not very clear and in these situations errors may occur.
In the third and fourth steps, a more rigid comparision of the template to potential matches is performed. In the third step, a coarse filter or match is conducted such as by using image pyramids. In the fourth step, a fine filter or match is performed using a pattern recognition algorithm. More particularly, gray-scale gradients for the template and the possible matches are computed using kernels of different sizes (i.e. n×n pixels). The dot products between the template gradients and the possible match gradients are computed. The results of the dot products undergo morphological dilation and order statistics are performed. If the sums of the order statistics are less than a predefined threshold, the possible match is determined to be a high probability match.
Once a list of the high probability matches has been obtained, the '665 patent family process identifies the input and output (I/O) pins on the high probability matches by mapping the coordinates of the I/O pins of the template to the high probability matches.
While the '665 patent family process uses a comparison scheme appropriate for the quality of image data obtained, among other disadvantages, the '665 patent family process does not incorporate other types and/or sources of data into the process. The '665 patent family process selects the standard cell manually. The '665 patent family process is limited to the imaging of metal layers and does not image non-metal layers such as polysilicon. Further, the '665 patent family process is limited to the identification of a standard cell and does not identify specific functions of the standard cell, such as for example connectivity of the standard cell and a transistor netlist of the integrated circuit.